The a 32-bit RISC-V CPU with M, Zicsr extensions, and External Debug support.

Includes:

- A five-stage pipeline,
- Harvard architecture
- Flexible size of program and data memory together with their allocation in address space.

The solution offers performance tailored to the project requirements, starting from:
- Dhrystone: up to 1,15 DMIPS/MHz
- Coremark: up to 2,36 CoreMark/MHz
- Area utilization: from 14k gates
- It is possible to select CPU interface as: AXI, AHB, Native.

The Core was developed as ISO26262 Safety Element out of Context (SEooC) and is technology
independent, and compatible with all FPGA and ASIC vendors.

The Core can be used along with a wide range of peripherals, like e.g. DMA, SPI, UART, PWM, CAN etc. This holistic approach makes the Core a good choice for application for e.g. Automotive, Internet of Things, Embedded, Consumer Electronics, and more.

The Core is a 32-bit core with 32 General Purpose Registers. It performs arithmetic and logic instructions, loads, stores, conditional branches, and unconditional jumps. The proper usage of base instructions provides an additional set of pseudo instructions which are available in the RISC-V assembly language. The M extension enables the use of additional integer multiplication and division instructions due to Multiplication and Division unit, which is responsible for
handling these instructions. The Zicsr extension provides the means to access Control and Status Registers, which in turn enables interrupt and exception handling according to version 20211203 of The RISC-V Instruction Set Manual Volume II: Privileged Architecture. With Zicsr extension Core is also equipped with performance counters and timers. External Debug support utilizes JTAG debug interface and is implemented with conformance to the RISC-V Debug Specification 0.13.2 and 1.0.0. That allows core debugging with all the tools compatible with this specification available on the market.

The Core is delivered with a fully automated test bench and a complete set of tests, allowing easy package validation at each stage of the SoC design flow.