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Layout/Backend IP Cores Consultancy Analog/Mix Design Turnkey ASIC
 
 

Dear ,

 

We are wishing you prosperity and success in 2026!

 

In this newsletter we would like to introduce you with a new IP core for ASIC/FPGA:

 

A High-Performance MIPI I3C Host Controller IP Core

Designed as a drop-in, higher-bandwidth, lower-power alternative to I²C and SPI, the IP brings robust performance and scalability to designs that depend on increasingly dense arrays of sensors and actuators. The IP fully conforms to MIPI I3C Basic v1.1.1 and demonstrates general compliance with the MIPI I3C HCI Specification 1.1, making it ideal for SoC teams preparing for next-generation architectures.

At up to 12.5 MHz operation, the IPI supports I3C SDR and HDR-DDR modes, while remaining fully backward compatible with I²C. Power efficiency is enhanced through optional clock gating, and throughput is optimized via configurable buffer sizes, programmable DAT/DCT structures, and a DMA handshake interface.

Key Features:

- Full compliance with MIPI I3C Basic v1.1.1

- General compliance with MIPI I3C HCI Specification 1.1

- Up to 5 MHz clock frequency

- Support for I3C SDR and I3C HDR-DDR modes

- Legacy I²C communication compatibility

- Dynamic Address Assignment (DAA)

- In-Band Interrupts and Hot-Join

- Common Command Codes (CCC)

- Configurable FIFO and memory buffers

- Configurable DAT/DCT (up to 16 slots)

- DMA handshake interface

- Power-efficient design with optional clock gating

- Memory-mapped interface with available wrappers:

- AMBA APB / AHB / AXI

- Altera Avalon

- Xilinx OPB

Engineered for Fast, Low-Risk Integration

To help teams accelerate project timelines, DI3CM-HCI ships with extensive documentation, synthesis scripts, reference implementations, and support options. Ready-to-use bus wrappers enable seamless deployment across FPGA prototypes and ASIC production environments.

Target Applications

The IP is optimized for designs where efficient peripheral communication, low power consumption, and tight latency control are critical. Key application domains include:

 > IoT and Edge Devices

Ideal for sensor-rich platforms such as smart home hubs, environmental monitors, wearables, industrial IoT nodes, and battery-powered edge devices. I3C’s lower power profile extends device lifetime while maintaining high data integrity across multiple sensors.

 > Consumer Electronics

Suitable for smartphones, tablets, AR/VR headsets, smart appliances, and human–machine interfaces where compact, high-throughput interconnects are essential for responsiveness and user experience.

 > Automotive & Transportation Systems

Applicable in ADAS units, driver-monitoring systems, cabin environmental sensing, powertrain controllers, and safety-critical sensor clusters. Backward compatibility with I²C helps OEMs migrate legacy platforms without redesigning entire subsystem chains.

>  Industrial & Robotics

Supports robotics systems, automation controllers, predictive maintenance sensors, and motor-control applications. The DMA handshake and configurable FIFOs ensure deterministic throughput even in real-time workloads.

> Medical & Health Monitoring Equipment

Suited for portable diagnostic devices, multi-sensor monitoring systems, wearable medical electronics, and equipment requiring low-noise, reliable sensor data streaming.

>  FPGA- and ASIC-Based Prototyping

Thanks to its configurable interface wrappers (AMBA/APB/AHB/AXI, Avalon, OPB), DI3CM-HCI can be integrated into any SoC architecture, speeding up prototype development and reducing system-level risk.

Across all these segments, the IP enables engineers to replace slow, power-heavy legacy buses with a modern, synchronized, feature-rich interface that keeps pace with next-generation embedded system requirements.

Info Request
 

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